FIG. 1 is a perspective view of a prior art power semiconductor device 100. The power semiconductor device 100 comprises a power semiconductor device package 110. The device package 110 comprises a silicon die 120 partially or wholly encased within a molding compound 130. Typically, power semiconductor devices are operated in extreme conditions. When a high current is run through the device 100, heat is generated in the silicon die 120. The device 100 requires that the heat be removed efficiently. In most cases, a heat sink 140 is applied to the device package 110 as a heat extractor. In order to let the heat sink 140 contact the silicon die 120 directly, the silicon die 120 needs to be exposed from its package, as shown in FIG. 1.
FIG. 2 is a transparent view of the prior art power semiconductor device package 110, showing an X-rayed view of the device package 110. Typically, the device package 110 works with high electrical current. Most of the time, a flip chip die, such as die 120, is used for such a device. The flip chip die uses connector balls 255 to connect the silicon die to a leadframe 215.
FIGS. 3A-C illustrate different stages of a prior art flip-chip process used to place a semiconductor die 320 on a leadframe 315. In FIG. 3A, tacky soldering flux 350 is placed in a flux equalizer tray 360. A flux equalizer squeegee 370 then sweeps the flux 350 in order to level off its height along the tray 360. A pick-and-place arm 380 holds the die 320, dipping its connector balls or bumps (disposed on the underside of the die) into the thin film of flux 350, which is typically about ½ to ⅔ of the height of the bumps or a minimum of 25 microns, depending on the bump size. The consistency of the thickness of the film 350 across the area in which the bumps are immersed is critical. The more coplanar the die and bumps are, the more flexible the planarity requirements of controlling and maintaining the flux film thickness. In FIG. 3B, the pick-and-place arm 380 places the die 320 on the leadframe strip 315. At this step, the die 320 is adhered onto the leadframe 315 by flux viscosity. FIG. 3C shows the leadframe strip 315 after it has been reflowed. The solder flux activates and melts the solder bumps, thereby bonding the bumps and, as a result, the die 320 to the leadframe 315.
FIG. 4A illustrates a stand-off height between a flip-chip die 420 and a leadframe 415. This stand-off height should be controlled when the die 420 is passed through the reflow process. As previously mentioned, during the reflow process, the solder bumps 455 are melted and bonded to the leadframe 415. In order to achieve a properly exposed die, such as shown in FIG. 1, the stand-off height needs to be precisely achieved at a certain value at all points of the package.
FIGS. 4B-C illustrate improper stand off height between the flip-chip die 420 and the leadframe 415. In certain situations, something goes wrong in the fabrication process and the stand-off height cannot be controlled. In FIG. 4B, after the unit has passed through the reflow process, one side of the die 420 has collapsed bumps 457, while the other side has almost un-melted bumps 455′. As shown in FIG. 4C, if the unit with collapsed bumps passed through the molding process, the molding compound 430 would cover the collapsed part of the die 420 under the level of mold thickness. As a result, the device package 410 would not be able to be used because the contact area of the exposed die 420 would not fully contact the heat sink.
FIG. 5A is a perspective view of a flip-chip die 520 being dipped into soldering flux 550 in a tray 560. Plane 5B is a virtual cutting plane used to illustrate the cross-sectional view of FIG. 5B. As seen in FIG. 5B, the connector balls 555 of the flip-chip die 520 are partially dipped into the flux 550.
FIG. 6A is a perspective view of the flip-chip die 520 being placed onto a leadframe 615. Plane 6B is a virtual cutting plane used to illustrate the cross-sectional view of FIG. 6B. As seen in FIG. 6B, flip-chip die 520 is placed onto the leadframe 615 with the flux-coated portion (shaded) of the connector balls 555 being placed in direct contact with the leadframe 615.
FIGS. 7A-C illustrate a good process for bonding a semiconductor die 720 to a leadframe 715. In FIG. 7A, the connector bumps 755 of the semiconductor die 720 are dipped into soldering flux 750 in a tray 760. Here, the flux level is uniform. In FIG. 7B, the die 720 is placed on the leadframe 715 before the reflowing process. The flux-coated portion (shaded) of the connector bumps 755 are placed in direct contact with the leadframe 715. Here, the flux level on the bumps 755 is uniform. In FIG. 7C, after the reflowing has been performed, the melted bumps 755′ connect the die 720 to the leadframe 715. Here, the melting of the bumps 755′ is uniform. When consistency of the flux thickness across the area in which the bumps 755 are immersed is accomplished, good uniform bump melting after reflowing is achieved. As a result, the exact desired stand-off height is achieved at all points.
FIGS. 8A-D illustrate a bad process for bonding a semiconductor die 820 to a leadframe 815. FIG. 8A shows the connector bumps 855 of the die 820 being dipped into soldering flux 850 in a tray 860 where the flux level is not uniform throughout the tray 860. FIG. 8B shows the connector bumps 855 of the die 820 being dipped into soldering flux 850 in a tray 860 where the die 820 and the flux level are not coplanar (e.g., if the die 820 is dipped at an angle). As seen in FIG. 8C, as a result of either the non-uniform flux level or the non-coplanarity between the die 820 and the flux level, there is an insufficient amount of flux on some of the connector bumps and excessive flux on other connector bumps and, in some case, on the die itself. The die 820 is placed on the leadframe 815. A reflowing process is then performed. FIG. 8D shows the die 820 on the leadframe 815 after the reflowing process has been performed, with the melted bumps 855′ connecting the die 820 to the leadframe 815. The connector bumps that had an insufficient amount of flux end up being almost un-melted after the reflowing process, whereas the connector bumps that had excessive flux end up collapsing, thereby resulting in an uneven melting of the connector bumps. Here, the vulnerability of the prior art is evident. If the consistency of the flux film thickness and coplanarity of the die and flux level are not achieved during flux dipping, then the crucial stand-off height at all points cannot be maintained after reflowing.